M.Tech VLSI Design @ Amrita
VLSI Design Engineer
RTL Design & Verification
Analog/Mixed-Signal IC Design
I am an Electronics & Communication graduate, now pursuing an M.Tech in VLSI Design at Amrita Vishwa Vidyapeetham. I work across the silicon stack — from RTL that verifies cleanly, to custom layouts that pass DRC/LVS, to device simulation I can trust.
Digital: Verilog/SystemVerilog RTL design with self-checking testbenches and waveform verification in QuestaSim/ModelSim — flip-flop families, counters, and an ALU, every one verified rather than just simulated. Analog/Custom: schematic capture, layout, DRC/LVS, parasitic extraction and post-layout simulation in Cadence Virtuoso. Device/TCAD: semiconductor device simulation in Synopsys Sentaurus across a material-engineered PN diode study and photodiodes in Si, Ge, GaAs and 4H-SiC.
The part of IC design most people skip is verification — it is the part that catches real bugs, and it is what I obsess over. I also mentor RTL and firmware workshops with the IEEE SSCS Student Branch.
IEEE SSCS Student Branch · Part-time
Mentor hands-on RTL, firmware, and electronics-simulation workshops for the IEEE Solid-State Circuits Society student branch — including sessions on Verilog, embedded design, and simulation tooling.
IEEE Student Branch, Sree Buddha College of Engineering
Coordinate technical events, workshops, and community initiatives for the IEEE student branch. Manage official communications, documentation, and collaboration across committees.
Nuke Labs · Kochi, Kerala
Own hardware architecture → firmware → bring-up for robotics, IoT and UAV systems at Nuke Labs. Full-time previously, part-time now while pursuing an M.Tech in VLSI Design.
Jawahar Navodaya Vidyalaya, Chennithala
Mentor school students in robotics, IoT, and design thinking through hands-on innovation sessions at the Atal Tinkering Lab, guiding them in building prototypes and problem-solving projects.
IEEE Student Branch, Sree Buddha College of Engineering
Organized and managed technical programs, workshops, and student engagement activities while coordinating with IEEE members and external speakers.
Entrepreneurship Cell (E-Cell), Sree Buddha College of Engineering
Led a student team to promote entrepreneurship by organizing startup-focused events, workshops, and guest lectures with industry professionals.
D, JK, SR, T flip-flops + ALU in Verilog/SystemVerilog
Constrained-random env + functional coverage for ALU
Material-engineered diode across Si, Ge, GaAs & 4H-SiC
Gate-All-Around device deck & performance analysis
Silicon PN junction — SDE scheme + SDevice deck
I-V & recombination across Si/Ge/GaAs/4H-SiC
Embedded networking firmware in C
MAX7299 clock with CPU/RAM monitor display
Raspberry Pi + CV smart waste segregation
VLSI Design Engineer (M.Tech) | RTL & Analog IC Design | Embedded Systems Engineer @ Nuke Labs
Kerala, India · 500+ connections
Embedded Systems Engineer
Nuke Labs · Part-time
Jan 2024 – Present
SSCS Mentor, IEEE
IEEE SSCS Student Branch
Apr 2026 – Present
Secretary, IEEE Student Branch
IEEE SB SBCE
Jan 2025 – Apr 2026
ATL Lab Instructor
Jawahar Navodaya Vidyalaya
Oct 2025 – Apr 2026
Embedded Systems Engineer
Freelance
2023 – Present
Amrita Vishwa Vidyapeetham
M.Tech, VLSI Design
2024 – Present
Sree Buddha College of Engineering
B.Tech, Electronics & Communication
2022 – 2026
Ananthakrishnan S
Kerala, India
Pinned repositories
Material-engineered PN diode — Si, Ge, GaAs & 4H-SiC
3-stack Nanosheet GAA-NMOSFET deck & analysis
2D silicon PN junction TCAD deck
ESP32 Ethernet via W5500 — embedded C
This portfolio site — VLSI focused
Contribution activity
